1. Field of the Invention
This invention relates to memory circuits and, more particularly, to improved first-in/first-out FIFO memory circuits.
2. Prior Art
A FIFO memory circuit is a data storage device which allows data information to be written into data-storage locations at a write-data rate. The data is read out of the data-storage locations at a read-data rate. A FIFO is arranged so that he data which is first written into the storage device is read out of the storage first, hence, the name FIFO. FIFO memories are often provided as semiconductor integrated-circuit devices. A FIFO is similar to a shift register because data enters and exits the device in the same order. However, from a circuit configuration point of view, there are some differences.
In a shift register, the data information is transferred from memory cell to memory cell so that the data information bits are not stored in a particular memory location., that is, data is serially "pushed" through a connected string of various memory cells. In a shift register, the memory cells are arranged in a string so that the data-output terminal of a first memory cell is connected to the data-input terminal of an adjacent cell. Sometimes, only the input terminal of the first memory cell in the string is externally available and only the output cell of the last memory cell in the string is externally available.
In a FIFO, each bit of data information is stored in a particular memory cell. In a FIFO the input terminals and the output terminals of each cell are externally available for writing data information directly into the next available cell and for reading data information directly out of the memory cell with the "oldest", or first-written, data information. In this sense, a FIFO memory is a more complex system than a shift register. In a FIFO, a read-address pointer keeps track of the address of the first-written information and a write-address pointer keeps track of the next available memory location into which the next information is to be written. The data for a particular FIFO cell goes directly into a memory cell from the input terminal of the FIFO. Data from the memory cell goes directly to the output terminal of the FIFO memory without being serially transferred from cell to cell. Reading and writing of data with a FIFO can be controlled by separate clock signals.
FIFO memory circuits are commonly used to buffer asynchronous data where the recipient of the data is sometimes unable to immediately receive or handle incoming data. For example, a FIFO memory could be used to buffer, or temporarily store, asynchronous input information from a keyboard for a computer system. Using a FIFO memory, if the computer system is not ready to accept keyboard information as it is generated in real time from the keyboard, the FIFO memory records the asynchronous keyboard information in the order that it was received and makes that keyboard information immediately available at any subsequent time that the computer system is ready to accept keyboard information.
A useful mechanical analogy to a FIFO memory is a coin-handling mechanism for a coin-operated vending-machine. In this analogy, a coin in the coin-holding mechanism of the vending machine is analogous to a data information bit stored in a FIFO memory location. Coins inserted by a user and stored in the coin-holding mechanism can be diverted to a coin-return slot (analogous to the data-output terminal of the FIFO) and asynchronously returned to the user by the user making a request for a return of the coin, prior to the user entering his or her selection into the vending machine. The time required for coins to fall from the coin-holding mechanism to the coin-return slot, or output, is analogous to the "read access delay time" of a FIFO memory device.
Typically, a FIFO memory includes an array of latches which have all of their their input terminals connected in parallel. The output terminals are also connected in parallel using, for example, tri-state output devices. Write-pointer logic is provided for addressing the next available memory location into which information can be written. Read-pointer logic is provided for addressing the memory location which has the earliest time of storage and which is to be read first. Status flags are provided to indicate the status of the FIFO memory, for example, full, half-full, or empty. In a typical FIFO, the FIFO-access time is the sum of the delays for the pointer-logic and the latch-array, that is, the elapsed time between initiation of a system read or write control trigger signal and the completion of a read or write operation.
Previously, efforts to improve the access time of a FIFO memory system have been focused on decreasing the circuit time-delays in both the pointer logic circuits and the latch memory arrays by using improved semiconductor integrated-circuit processing techniques and process technologies to provide faster individual circuit elements of the FIFO memory system.
A need exists for improving the operating speed of a FIFO memory system in order to reduce overall access time to the FIFO. At the same time, it is desireable that no major changes be made to the circuit designs of the circuit elements of the memory system or to the support circuitry used with a conventional FIFO memory system.